Inferring two multipliers in one DPS block in verilog/VHDL, Cyclone V

Rather than filling an FPGA until all of its DSP resources are used, you can use logiclock to force the design into a smaller area.

If for example, you expect to fit two multipliers into a single DSP block, and you have used the appropriate DSP block inference HDL code, then it will work. If it does not, then I would first recommend instantiating an IP Catalog instance and confirm that you can get the DSP logic packed into a single block. Then go and use the templates provided in the Quartus II editor (assuming there is some DSP logic close to what you want). Basically you'll need to "debug" why your inference code is not working. It could be something simple like the use of a reset control in your HDL that does not exist in the underlying resource. I'd recommend dumbing-down your design until it packs correctly, and then edit and synthesize to determine what additional logic causes it to fail.

Cheers,

Dave