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Honored Contributor
Honored ContributorInferring two multipliers in one DPS block in verilog/VHDL, Cyclone V
The module dsp1a infers two DSP blocks. Why not one DSP? Is there any way to force synthesiser to use one DSP block? I would like to use Independent Multiplier Mode of DSP block. While the si...
Altera_ForumHonored Contributor
Honored ContributorThank you for reply. But I tried inferring 26 multipliers on device having 25 DSP blocks and it not fit. So automatic merging multipliers to DSP seems doesn't occur. I tried also different speed/balance optimization.
