Inferring two multipliers in one DPS block in verilog/VHDL, Cyclone V

The module dsp1a infers two DSP blocks. Why not one DSP? Is there any way to force synthesiser to use one DSP block?

I would like to use Independent Multiplier Mode of DSP block.

While the similar module dsp1a+dsp1b (top level is now dsp1b) uses one DSP block, as expected.

module dsp1a(input wire [7:0] a1, input wire [7:0] b1,

input wire [7:0] a2, input wire [7:0] b2,

output wire [15:0] y1,

output wire [15:0] y2

);//infers 2 DSP when top-level: BAD

assign y1 = a1 * b1;

assign y2 = a2 * b2;

endmodule

module dsp1b(input wire [7:0] a1, input wire [7:0] b1,

input wire [7:0] a2, input wire [7:0] b2,

output wire [15:0] y

);//infers 1 DSP when top-level: OK

wire [15:0] y1;

wire [15:0] y2;

dsp1a dsp1 (.a1(a1), .b1(b1), .a2(a2), .b2(b2), .y1(y1), .y2(y2));

assign y = y1 + y2;

endmodule

Thanks in advance