Inferring two multipliers in one DPS block in verilog/VHDL, Cyclone V

I am having a similar problem where I have 8 9x9 multipliers and their outputs are fed into an adder tree to get the sum of products.

I was hoping Quartus to use only 3 DSP blocks, where 2 DSPs are in "three independent 9x9" mode and 1 DSP in "three indepedent 9x9" or "two 18x18" mode.

However, Quartus manages to use 4 DSPs with 2 sets of cascaded "sum of four 18x18" blocks (2 DSP for each four 18x18).

I tried setting a logic lock region which has 3 DSPs and sufficient amount of LUTs for the adder tree, but Quartus complains unable to fit.

Hope Quartus can provide more fine-grained controls to users in this case.