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Altera_Forum
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10 years ago

Inferring two multipliers in one DPS block in verilog/VHDL, Cyclone V

The module dsp1a infers two DSP blocks. Why not one DSP? Is there any way to force synthesiser to use one DSP block? I would like to use Independent Multiplier Mode of DSP block. While the si...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

Hi,

I'm having a similar problem, our design fails to fit with an error about too many dsp elements but it should easily fit when packing 2 18x18 / 3 9x9s in each dsp...

I found that by setting the 'Auto pack registers' under fitter settings to Off (the default is Auto i think), the design now fits. it seems like its packing registers in to the dsps before it actually packs the multipliers in... or something...

Would be good to get a proper fix as register packing is useful to have on.

Hope it helps,

Cheers

Adam