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Honored Contributor
Honored ContributorInferring two multipliers in one DPS block in verilog/VHDL, Cyclone V
The module dsp1a infers two DSP blocks. Why not one DSP? Is there any way to force synthesiser to use one DSP block? I would like to use Independent Multiplier Mode of DSP block. While the si...
Altera_ForumHonored Contributor
Honored Contributorpls try to create a simple design which consist only three multipliers 9x9 and then logic lock this design with a region that consist only one DSP block. It should work.
