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Altera_Forum
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10 years ago

Inferring two multipliers in one DPS block in verilog/VHDL, Cyclone V

The module dsp1a infers two DSP blocks. Why not one DSP? Is there any way to force synthesiser to use one DSP block? I would like to use Independent Multiplier Mode of DSP block. While the si...
Altera_Forum's avatar
Altera_Forum
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10 years ago

Hi Luca,

still I have not good news. If I find the solution, I will write it here.

Cheers, Jan

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Hi all,

I am facing the same issue of jenii. Both Quartus v14 and v15 does not pack three multipliers 9x9bit within the same DSP block. I tried also with the lpm_mult and altmult instances with no luck.

Jenii, have you got any news from Altera?

Cheers,

Luca

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