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Honored Contributor
Honored ContributorInferring two multipliers in one DPS block in verilog/VHDL, Cyclone V
The module dsp1a infers two DSP blocks. Why not one DSP? Is there any way to force synthesiser to use one DSP block? I would like to use Independent Multiplier Mode of DSP block. While the si...
Altera_ForumHonored Contributor
Honored Contributordo you mean that you are using 26 independent 8x8 multiples? did you see fitting error or any other errors? How many DSP blocks are occupied?
