Inferring two multipliers in one DPS block in verilog/VHDL, Cyclone V

--- Quote Start ---

Thank you. I tried: verilog and VHDL modules with configurations that matched DSP block schematic (seen both in Chip Planner and in datasheet [1]), recommended coding styles, templates, multiplier drawn in BDF schematic, altera lpm_mult IP functions. In every case the result was 2 DSP blocks.

--- Quote End ---

Sounds like you have tried everything :)

--- Quote Start ---

But in [1], table 3-4 on page 49 it is shown that DSP block supports three 9x9 multiplications in independent configuration. Now I am trying to explicitly pack DSP input registers (three 9bit -> 27bit input), without success.

[1] https://www.altera.com/content/dam/altera-www/global/en_us/pdfs/literature/hb/cyclone-v/cv_5v2.pdf

--- Quote End ---

File a Service Request with Altera directly. They were the ones who suggested I try LogicLock when I had a similar question. Hopefully they can help you with this question.

Cheers,

Dave