Hi dears: I am using ArriaGX devices, and the board's clock is 100Mhz which is input to the FPGA. And the system need a 45MHz clock, could you have any method to generate this clock through FPGA's PLL? Otherwise i have to use aonther 45Mhz oscillator. Thanks! Jerry

use megafunction wizard. [tools] -> [megawizard plug-in manager] [create a new custom megafunction variation] -> [Next] [I/O] -> [ALTPLL]

It shouldn't be a problem for the Arria's PLL, with a VCO frequency of 450MHz it should be able to do it.

Hi guys: In fact, I know how to implement PLL using QII. My question is that the ArriaGX's PLL couldn't get a output of 45Mhz when the Pll's input is 100Mhz. Thanks Jerry

--- Quote Start --- I know how to implement PLL using QII. My question is that the ArriaGX's PLL couldn't get a output of 45Mhz when the Pll's input is 100Mhz. --- Quote End --- Basically 100MHz input and 45 MHz does work. But, the LCM (Least Common Multiple) of the input clock and all output clocks must be in the range of the PLL's VCO, e.g. at 100MHz input, and outputs of 45MHz and 80MHz the VCO needs to run at 3.6 GHz, where the allowable range only is 600 to 1400 MHz.

Why not use clken at 45MHz using clock 100MHz as system clock, if it is for inside fpga processing? If it is for outside fpga you can try 90MHz or 180 ...etc and divide internally then use ddr to pass 45 out

How to get 45Mhz clock out? | Altera Community

27 Replies

Altera_Forum
Honored Contributor
14 years ago
I have used this method for various projects esp. when upsampling data by variable fractions towards the DAC rate. symbol rate may vary in systems and need be uplifted to DAC rate. on the same fixed system clock I generate an enable "backpressure" from upsampler module running at system clock to request data at its lower rates.
Altera_Forum
Honored Contributor
14 years ago
(I think we are going a bit off-topic here ... continuing regardless)
I assume there is some clock domain crossing involved going from a low input rate to the high output rate? Then I see a dcfifo in the path which does this rate adapting automatically? Or do you think this produces more jitter?
Altera_Forum
Honored Contributor
14 years ago
No, we are talking about one clock domain. The 100Mhz will clock all the registers conditioned on clken to slow it down to 45MHz rate.
There is no need for fifos since we are not talking about two clocks.
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
No, we are talking about one clock domain. The 100Mhz will clock all the registers conditioned on clken to slow it down to 45MHz rate.
There is no need for fifos since we are not talking about two clocks.
--- Quote End ---

Still puzzled where the 45 MHz rate comes from? As you are (e.g.) upsampling data from 45 MHz to 100 MHz, there must be a 45MHz clock (internal or external) involved as well?
Altera_Forum
Honored Contributor
14 years ago
it is the rate of 100MHz clock slowed down by invalid slots resulting in an effective rate of 45MHz from processing perspective.
If I run my upsampler on 100MHz, and my data is at 45MHz nominal rate then I will run data section on same 100MHz clock but conditioned on clken i.e. I will send request (= clken) backwards to read data and push it through upsampler. The upsampler is based on filters.

Passing domains has multiple meanings(depends on perspective):
1) ordinary two clock domain passing of data at its rate (no change of effective rate)
2) cross from one sampling rate to another by creating new samples or removing samples so that the signal carries same info (DSP perspective)
This same as if you use an ADC of say 112MHz to sample a signal that was originally on 76MHz.
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
and my data is at 45MHz nominal rate
--- Quote End ---

Where is the 45MHz nominal rate defined? I only see a 'virtual' 45MHz rate in a 100 MHz system where everything is running at a 100 MHz (avoiding clock domain crossing) and where you sub- or down-sample the incoming stream to this 'virtual' 45 MHz (using the described add/modulo technique) and then, after possibly performing mixing or other operations with other signals, upsample it back to 100 MHz. But if the input data is coming from e.g. a 45 MHz ADC there will be clock domain crossing involved, somehow?
Altera_Forum
Honored Contributor
14 years ago
There is really nothing new in my rate generator. It is the same issue as any other clock enable.
There are many designs we talk about that use clken and possibly 100s of posts about it.
The only difference is that I am talking about various schemes of enable generation itself.

The small details can only make sense in the context of a given application.
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
There is really nothing new in my rate generator. It is the same issue as any other clock enable.
There are many designs we talk about that use clken and possibly 100s of posts about it.
The only difference is that I am talking about various schemes of enable generation itself.

The small details can only make sense in the context of a given application.
--- Quote End ---

I was trying to understand what you are doing, and whether my first idea of the dcfifo was valid or flawed. I don't have a concrete application in mind yet. I may get back to you when the time comes.
Altera_Forum
Honored Contributor
14 years ago
For 2 async clocks crossing, you certainly need some logic work e.g. employing the dcfifo or your own logic. That is a separate issue.

Rate control is another, you can clock freely or clock constrained by fellow clken.
System clocks nowadays are so fast relative to sampling rate that time folding is very common and this makes designer life miserable with spaghetti logic.
Altera_Forum
Honored Contributor
14 years ago
--- Quote Start ---
System clocks nowadays are so fast relative to sampling rate that time folding is very common and this makes designer life miserable with spaghetti logic.
--- Quote End ---

I do not understand what you mean by this:
Either you make your life miserable creating spaghetti logic using rate control / time folding, or it is the others having a miserable life not using it?
I wouldn't compare a system using flow control to spaghetti logic ...
Yet again, you speak about two clocks, the system clock and the sampling rate. But you haven't explained to me where the sampling rate comes from.

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How to get 45Mhz clock out?

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