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Honored Contributor
Honored ContributorHow to get 45Mhz clock out?
Hi dears: I am using ArriaGX devices, and the board's clock is 100Mhz which is input to the FPGA. And the system need a 45MHz clock, could you have any method to generate this clock through FPG...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- and my data is at 45MHz nominal rate --- Quote End --- Where is the 45MHz nominal rate defined? I only see a 'virtual' 45MHz rate in a 100 MHz system where everything is running at a 100 MHz (avoiding clock domain crossing) and where you sub- or down-sample the incoming stream to this 'virtual' 45 MHz (using the described add/modulo technique) and then, after possibly performing mixing or other operations with other signals, upsample it back to 100 MHz. But if the input data is coming from e.g. a 45 MHz ADC there will be clock domain crossing involved, somehow?
