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Honored Contributor
Honored ContributorHow to get 45Mhz clock out?
Hi dears: I am using ArriaGX devices, and the board's clock is 100Mhz which is input to the FPGA. And the system need a 45MHz clock, could you have any method to generate this clock through FPG...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- No, we are talking about one clock domain. The 100Mhz will clock all the registers conditioned on clken to slow it down to 45MHz rate. There is no need for fifos since we are not talking about two clocks. --- Quote End --- Still puzzled where the 45 MHz rate comes from? As you are (e.g.) upsampling data from 45 MHz to 100 MHz, there must be a 45MHz clock (internal or external) involved as well?
