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Honored Contributor
Honored ContributorHow to get 45Mhz clock out?
Hi dears: I am using ArriaGX devices, and the board's clock is 100Mhz which is input to the FPGA. And the system need a 45MHz clock, could you have any method to generate this clock through FPG...
Altera_ForumHonored Contributor
Honored ContributorFor 2 async clocks crossing, you certainly need some logic work e.g. employing the dcfifo or your own logic. That is a separate issue.
Rate control is another, you can clock freely or clock constrained by fellow clken. System clocks nowadays are so fast relative to sampling rate that time folding is very common and this makes designer life miserable with spaghetti logic.
