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Honored Contributor
Honored ContributorHow to get 45Mhz clock out?
Hi dears: I am using ArriaGX devices, and the board's clock is 100Mhz which is input to the FPGA. And the system need a 45MHz clock, could you have any method to generate this clock through FPG...
Altera_ForumHonored Contributor
Honored Contributor(I think we are going a bit off-topic here ... continuing regardless)
I assume there is some clock domain crossing involved going from a low input rate to the high output rate? Then I see a dcfifo in the path which does this rate adapting automatically? Or do you think this produces more jitter?
