Help with metastability problem

Timing analysis is the way to find out about violations.

addr <= addr + 1;
count <= count + 1;

Hi,

I suggest before you go back to synthesis or timing analysis, get yourself a testbench written and run the design through modelsim, eliminating all of the latches (ie. make sure things like counters are inside a synchronous process, not the async one).

So I can remove all latches by moving the signals that store values inside the process that checks for the rising clock edge? I thought latches were inferred anytime a signal holds its current value.

latches are created when a value stores its value without using a clock. These are bad because they are prone to metastability, temperature and cannot be studied in timing analysis.

An other issue are the signals DVAL_IN, FVAL_IN and buffer_lock. If they are not synchronous to the clock you should/must synchronize them. Otherwise you will run into metastability problems with your fvalid_reg and lock_reg signal.

Thanks,

State-of-the-art is double-registering signals from unrelated clock domains. If you don't mind rare metastable events (the actual probability needs to be calculated), single registering can be O.K.

hey i've re-written my block and I don't get any more warnings from quartus.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.obj_extraction_pkg.all;
entity OBJ_RamWriter is
  port(
    -- Clock Input
    CLK : in std_logic;
    
    -- Inputs
    buffer_lock     : in std_logic  := '0';
    VALID_IN        : in std_logic  := '0';
    DVAL_IN         : in std_logic  := '0';
    FVAL_IN         : in std_logic  := '0';
    LINE_OBJ        : in std_logic_vector(obj_wd-addr_wd-1 downto 0);
    
    -- Outputs
    buffer_lock_out : out std_logic := '0';
    buffer_rdy      : out std_logic := '0';
    wren            : out std_logic := '0';
    wr_addr         : out unsigned(6 downto 0);
    obj_count       : out unsigned(6 downto 0);
    wr_data         : out std_logic_vector(obj_wd-addr_wd-1 downto 0)
  );
end entity;
architecture rt1 of OBJ_RamWriter is
  -- Data Registers
  signal line_reg   : std_logic_vector(obj_wd-addr_wd-1 downto 0);
  
  -- Internal States
  signal odd          : std_logic := '0';
  
  -- Output registers
  signal lock_out_reg   : std_logic := '0';
  signal valid_out_reg  : std_logic := '0';
  
BEGIN
	process (CLK)
		variable addr	:	unsigned(6 downto 0)	:=	to_unsigned(0,7);
		variable count	:	unsigned(6 downto 0)	:=	to_unsigned(0,7);
		variable ready	:	std_logic				:=	'0';
    BEGIN
      if (rising_edge(CLK)) then
			-- Store inputs
			lock_out_reg <= buffer_lock;
			if (buffer_lock = '0') then
				valid_out_reg <= '1'; --VALID_IN;
				if (DVAL_IN = '1' and FVAL_IN = '1') then -- Frame valid (writing state)
					if (ready = '1') then -- Was previously in upload state, reset
						ready := '0';
						if (VALID_IN = '1') then -- will be writing this cycle so initialise as such
							addr := to_unsigned(0,7);
							count := to_unsigned(1,7);
						else -- nothing to write this cycle initialise as such
							addr := b"1111111";
							count := to_unsigned(0,7);
						end if;
					else -- not reset case
						ready := '0';
						if (VALID_IN = '1') then -- writing this cycle
							addr := addr + 1;
							count := count + 1;
						else -- nothing to do
							addr := addr;
							count := count;
						end if;
					end if;
				else -- Uploading State
					ready := '1';
					valid_out_reg <= '0';
					addr := addr;
					count := count;
				end if;
				if (odd = '0') then
					odd <= '1';
					line_reg <= std_logic_vector(to_unsigned(4, 8) & to_unsigned(1,10) & to_unsigned(1,10) & to_unsigned(1,10) & to_unsigned(1,10));--LINE_OBJ;
				else
					odd <= '0';
					line_reg <= std_logic_vector(to_unsigned(4, 8) & to_unsigned(1,10) & to_unsigned(1,10) & to_unsigned(1,10) & to_unsigned(2,10));
				end if;
			else -- Locked by buffer_lock keep same state
				valid_out_reg <= '0';
				ready := ready;
				addr := addr;
				count := count;
				line_reg <= line_reg;
				odd <= odd;	
			end if;
      end if;
		buffer_rdy <= ready;
		wr_addr <= addr;
		obj_count <= count;
  end process;
  
  buffer_lock_out <= lock_out_reg;
  wren <= valid_out_reg;
  wr_data <= line_reg;   
end rt1;
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.obj_extraction_pkg.all;
entity OBJRam_test is
end OBJRam_test;
architecture bench of OBJRam_test is
  component OBJ_RamWriter
    port (
        -- Clock Input
        CLK : in std_logic;
    
        -- Inputs
        buffer_lock     : in std_logic  := '0';
        VALID_IN        : in std_logic  := '0';
        DVAL_IN         : in std_logic  := '0';
        FVAL_IN         : in std_logic  := '0';
        LINE_OBJ        : in std_logic_vector(obj_wd-addr_wd-1 downto 0);
    
        -- Outputs
        buffer_lock_out : out std_logic := '0';
        buffer_rdy      : out std_logic := '0';
        wren            : out std_logic := '0';
        wr_addr         : out unsigned(6 downto 0);
        obj_count       : out unsigned(6 downto 0);
        wr_data         : out std_logic_vector(obj_wd-addr_wd-1 downto 0)
    );
  end component;
  
  signal CLK, buffer_lock, VALID_IN, DVAL_IN, FVAL_IN, buffer_lock_out, buffer_rdy, wren  : std_logic;
  signal wr_addr, obj_count                                                               : unsigned(6 downto 0);
  signal LINE_OBJ, wr_data                                                                : std_logic_vector(obj_wd-addr_wd-1 downto 0);  
  
BEGIN
  
  clk_process :process
  begin
    CLK <= '0';
    wait for 100 PS;
    CLK <= '1';
    wait for 100 PS;    
  end process;
  
  stim_process :process
  begin
    VALID_IN <= '0';
    FVAL_IN <= '1';
    DVAL_IN <= '1';
    buffer_lock <= '1';
    LINE_OBJ <= b"000000000000000000000000000000000000000000000000";
    wait for 150 ps;
    VALID_IN <= '0';
    FVAL_IN <= '1';
    DVAL_IN <= '1';
    buffer_lock <= '0';
    LINE_OBJ <= b"100000000000000000000000000000000000000000000000";
    wait for 200 ps;
    VALID_IN <= '1';
    FVAL_IN <= '1';
    DVAL_IN <= '1';
    buffer_lock <= '0';
    LINE_OBJ <= b"010101010101010101010101010101010101010101010101";
    wait for 200 ps;
    VALID_IN <= '1';
    FVAL_IN <= '1';
    DVAL_IN <= '1';
    buffer_lock <= '0';
    LINE_OBJ <= b"110101010101010101010101010101010101010101010101";
    wait for 200 ps;
    VALID_IN <= '0';
    FVAL_IN <= '1';
    DVAL_IN <= '1';
    buffer_lock <= '0';
    LINE_OBJ <= b"111101010101010101010101010101010101010101010101";
    wait for 200 ps;
    VALID_IN <= '1';
    FVAL_IN <= '1';
    DVAL_IN <= '1';
    buffer_lock <= '0';
    LINE_OBJ <= b"111111010101010101010101010101010101010101010101";
    wait for 200 ps;
    VALID_IN <= '1';
    FVAL_IN <= '0';
    DVAL_IN <= '0';
    buffer_lock <= '0';
    LINE_OBJ <= b"111111110101010101010101010101010101010101010101";
    wait for 200 ps;
    VALID_IN <= '0';
    FVAL_IN <= '1';
    DVAL_IN <= '1';
    buffer_lock <= '0';
    LINE_OBJ <= b"111111110101010101010101010101010101010101010101";    
    -- wait for 200 ps;
    
    wait;
  end process;
  
  M:  OBJ_RamWriter port map (CLK, buffer_lock, VALID_IN, DVAL_IN, FVAL_IN, LINE_OBJ, buffer_lock_out, buffer_rdy, wren, wr_addr, obj_count, wr_data);
  
end bench;

Although not strictly a problem in RTL simulation, you would want to operate the testbench at a speed that can be processed by a real FPGA.