Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorHelp with metastability problem
Hi, I'm working on a vision processing based project at uni using a custom board built around a cyclone III and I am having to modify some vhdl code written by previous years students. A met...
Altera_ForumHonored Contributor
Honored ContributorState-of-the-art is double-registering signals from unrelated clock domains. If you don't mind rare metastable events (the actual probability needs to be calculated), single registering can be O.K.
Using variables for intermediate results in a synchronous process means to chain more logic elements and reduce maximum design speed. As long as you have sufficient timing margin, there's no problem involved.
