Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorHelp with metastability problem
Hi, I'm working on a vision processing based project at uni using a custom board built around a cyclone III and I am having to modify some vhdl code written by previous years students. A met...
Altera_ForumHonored Contributor
Honored ContributorI suggest before you go back to synthesis or timing analysis, get yourself a testbench written and run the design through modelsim, eliminating all of the latches (ie. make sure things like counters are inside a synchronous process, not the async one).
