Inquiry About Package Internal Trace Lengths of Arria 10 PCIe Pins

I referred to the following document to check the package internal trace lengths of the pins on the Arria 10 FPGA.

Device: 10AX032E3F29E2LG

Reference document: 10AX032EF29_netlength.xlsx

However, I could not find the internal trace length information for the transceiver pins in this document.

Examples of the pins of interest include:

REFCLK_GXBL

GXBL1D_TX/RX

Could you please let me know if there is any documentation available that provides the package internal trace lengths for these transceiver pins?

If such documentation is not publicly available, could you recommend any reference materials or design guidelines that would be useful for PCB routing of these transceiver pins, particularly for considering package delay and trace length?