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Honored Contributor
Honored ContributorHelp with metastability problem
Hi, I'm working on a vision processing based project at uni using a custom board built around a cyclone III and I am having to modify some vhdl code written by previous years students. A met...
Altera_ForumHonored Contributor
Honored ContributorAlthough not strictly a problem in RTL simulation, you would want to operate the testbench at a speed that can be processed by a real FPGA.
I'm also not sure, if the design will keep up with the rapid input changes in terms of design clock cycles. But this can be more easily traced in simulation than in a code review.
