Help with metastability problem

So I can remove all latches by moving the signals that store values inside the process that checks for the rising clock edge? I thought latches were inferred anytime a signal holds its current value.

I have written a testbench and when simulating it in model sim it works as expected, but I will try to get rid of the counters and signals that maintain a value from the asynchronous process.

Any other comments on my code to help me improve would be greatly appreciated. I am reading books on VHDL concurrently as well however I have to learn as fast as possible as the project is time limited.

Thanks,

Mat.