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Altera_Forum's avatar
Altera_Forum
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14 years ago

Help with metastability problem

Hi, I'm working on a vision processing based project at uni using a custom board built around a cyclone III and I am having to modify some vhdl code written by previous years students. A met...
Altera_Forum's avatar
Altera_Forum
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14 years ago

An other issue are the signals DVAL_IN, FVAL_IN and buffer_lock. If they are not synchronous to the clock you should/must synchronize them. Otherwise you will run into metastability problems with your fvalid_reg and lock_reg signal.