Help with metastability problem

Hi,

Thanks for the reply, I know there are possible many things wrong with my code,

this is the first time I have ever used VHDL so it has been a bit of an experience to say the least. Quartus is spitting out warnings about inferred latches which I've read are a bad thing but i'm not sure how to design it any other way. Would you mind walking me through how you would go about designing this block (its a fairly simple block anyway)

Basically what I am trying to make the block do is

- Check if the frame data is valid by checking DVAL and FVAL

(If the frame data is valid I am writing to the RAM block otherwise I am waiting while the data is uploaded)

- Check if I am blocked (buffer_lock) and if so do nothing

Writing state

- if writing state just started (was previously uploading) reset the address and object count

- Check if the obj data coming in is valid by checking VALID_IN

- If data is valid write it to RAM and increment the address and object count

- If RAM is full, the object count is equal to the RAM size do nothing

Upload state

- send out the object count and ready signal

I'm also looking into timing analysis, as the output does seem like metastability

but I do agree there are other problems with my code.

Thanks,

Mat.