Help with metastability problem

Thanks,

DVAL and FVAL are external signals and are synchronized to the clock once at the input by passing through a clocked register. Is that enough or should that be re synchronized at certain points if they are used across large portions of the design. As far as buffer_lock i'm not 100% sure but i'll look into that. Thanks for the advice about inferred latches as well.

my current design was partly due to the concurrent and delayed nature of signal assignments, i have been looking into using variables instead of some of the signals so that I can assign some things sequentially, is this a good or bad idea?

Thanks,

Mat.