I normally reset all my d-types using their asynchronous input. I have done this for a long time without any issues. The other day I was chatting to someone else and he said it is best practice not to use the asynchronous input but use a synchronous reset instead. But he didn't know why. The problem I see with synchronous reset is it could make the set-up and hold time longer. Does anyone have any comments or advice on this subject? Thanks in advance. geobyjmh

If you have a asyncronious reset, which also clears asynchrone you might end up with some meta-stability after the reset, and you don't want this. You can prevent this by using a synchrone reset, but this gives troubles if you have a reseet affecting the clock, or timing problems. The solution I use is to trigger the reset asynchrone and then clock the clear through two flip-flops to get it synchronised. In this way you have the best of both worlds. [edit] attached is a RTL-viewer schematic of the circuit, but than with a dual-input high to trigger the reset. [/edit]

just have the async reset connected to a synchronous signal, then no problem with timing (or what pierter suggested above). Altera flops have no sync resets, so their behaviour has to be emulated with a mux. But it will make your code more portable, and slightly easier to read.

Thanks PietervanderStar. I like your solution! Your RTL looks interesting and is worth some considering. Does metastability affect the asynchronous input on a d-type? I didn't think they did because they are independent of the clock. However I think you solution is elegant and will probably start using it.

--- Quote Start --- Does anyone have any comments or advice on this subject? --- Quote End --- The choice of which HDL style to use should be influenced by the underlying architecture of the FPGA, or FPGA resource. For example, I recall an FPGA component (DSP block in Xilinx I think) that does not have an asynchronous reset. If you tried to code one, you either ended up with an error, or "extra" logic. The registers in Altera devices have asynchronous reset ports, so you should write your code such that it uses them. The caveat is that you need to synchronize the reset sources to each clock domain in your FPGA, i.e., use the reset synchronizer PietervanderStar posted. Cliff Cummings has several tutorials on synchronizing reset. TimeQuest will analyze your synchronized reset paths via the reset recovery and removal timing. If you write your code for a synchronous reset, then Quartus will create logic to implement your synchronous reset, i.e., you will needlessly use up LUT inputs. So the "cost" of using an incorrect style, is a larger design, and a potential to increase the combinatorial path in your design. I'd recommend reading the Cliff Cummings papers on resets ... http://www.sunburst-design.com/papers/ Cheers, Dave

Thanks Tricky. How would have though a reset signal could be so interesting :-) From what you have written does that mean you would use a mux on every flip flop in a design to give them all synchronous reset?

FPGA reset asynchronous or synchronous? | Altera Community

15 Replies

Altera_Forum
Honored Contributor
11 years ago
If you have a asyncronious reset, which also clears asynchrone you might end up with some meta-stability after the reset, and you don't want this. You can prevent this by using a synchrone reset, but this gives troubles if you have a reseet affecting the clock, or timing problems. The solution I use is to trigger the reset asynchrone and then clock the clear through two flip-flops to get it synchronised. In this way you have the best of both worlds.
[edit]
attached is a RTL-viewer schematic of the circuit, but than with a dual-input high to trigger the reset.
[/edit]
Altera_Forum
Honored Contributor
11 years ago
just have the async reset connected to a synchronous signal, then no problem with timing (or what pierter suggested above).
Altera flops have no sync resets, so their behaviour has to be emulated with a mux. But it will make your code more portable, and slightly easier to read.
Altera_Forum
Honored Contributor
11 years ago
Thanks PietervanderStar. I like your solution! Your RTL looks interesting and is worth some considering.

Does metastability affect the asynchronous input on a d-type? I didn't think they did because they are independent of the clock.

However I think you solution is elegant and will probably start using it.
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---

Does anyone have any comments or advice on this subject?

--- Quote End ---

The choice of which HDL style to use should be influenced by the underlying architecture of the FPGA, or FPGA resource.

For example, I recall an FPGA component (DSP block in Xilinx I think) that does not have an asynchronous reset. If you tried to code one, you either ended up with an error, or "extra" logic.

The registers in Altera devices have asynchronous reset ports, so you should write your code such that it uses them. The caveat is that you need to synchronize the reset sources to each clock domain in your FPGA, i.e., use the reset synchronizer PietervanderStar posted. Cliff Cummings has several tutorials on synchronizing reset. TimeQuest will analyze your synchronized reset paths via the reset recovery and removal timing.

If you write your code for a synchronous reset, then Quartus will create logic to implement your synchronous reset, i.e., you will needlessly use up LUT inputs. So the "cost" of using an incorrect style, is a larger design, and a potential to increase the combinatorial path in your design.

I'd recommend reading the Cliff Cummings papers on resets ...

http://www.sunburst-design.com/papers/

Cheers,
Dave
Altera_Forum
Honored Contributor
11 years ago
Thanks Tricky. How would have though a reset signal could be so interesting :-)

From what you have written does that mean you would use a mux on every flip flop in a design to give them all synchronous reset?
Altera_Forum
Honored Contributor
11 years ago
Thanks Dave - I will have a read of the papers. They look interesting.
Altera_Forum
Honored Contributor
11 years ago
There is a dedicated, LAB-wide synchronous reset, so it's not going to use up part of your LUT, but synthesis does try to push LUT logic onto the synchronous reset if it's available, so the net sum is it can make your design larger and slower if you have a synchronous reset. I have worked with users that have switched entire designs from synchronous to asynchronous, and the area savings was <2% and the performance savings was less than normal seed noise, so though I recommend asynchronous, it's not something that usually makes or breaks your design. (I've had users debating if they wanted to convert hundreds of old files that they really don't want to touch, and evaluate it wasn't worth the work).
Altera_Forum
Honored Contributor
11 years ago
Thanks Rysc. I found your comment very interesting. There is a lot more to reseting that I have ever considered. I have also been doing a little reading on the subject, hopefully I can will find time to summarize it. However this thread has provided some very useful pointers.
Altera_Forum
Honored Contributor
11 years ago
The recovery and removal section on page 65 should talk about reset structures:
http://www.alterawiki.com/wiki/timequest_user_guide
Altera_Forum
Honored Contributor
11 years ago
--- Quote Start ---
There is a dedicated, LAB-wide synchronous reset, so it's not going to use up part of your LUT
--- Quote End ---

Hi Rysc, just curious about above point. Wouldn't the lab wide reset also need gating?

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FPGA reset asynchronous or synchronous?

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