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Altera_Forum
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12 years ago

FPGA reset asynchronous or synchronous?

I normally reset all my d-types using their asynchronous input. I have done this for a long time without any issues. The other day I was chatting to someone else and he said it is best practic...
Altera_Forum's avatar
Altera_Forum
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12 years ago

Thanks PietervanderStar. I like your solution! Your RTL looks interesting and is worth some considering.

Does metastability affect the asynchronous input on a d-type? I didn't think they did because they are independent of the clock.

However I think you solution is elegant and will probably start using it.