Inquiry Regarding MAX 10 TDO Output Level During JTAG Operation

We would like to inquire about the TDO output level of a MAX 10 FPGA during JTAG operation.

Device:

- 10M08DCF256I7G

Test Configuration:

- Single MAX 10 device in the JTAG chain

- VCCIO1B = 3.3 V (measured)

- VTREF = 3.3 V (measured)

- TDO measured directly at the FPGA pin using an oscilloscope

- Tested with both USB-Blaster and USB-Blaster II

- Same behavior observed on multiple boards

Observed Behavior:

- With the USB-Blaster disconnected:

- TDO High level is approximately 3.3 V

- With the USB-Blaster connected:

- TDO High level is approximately 2.5 V

- TDO Low level is approximately 0 V

- TDO toggles normally during JTAG communication

JTAG Functionality:

- Auto Detect succeeds

- Device programming succeeds

- Verify succeeds

Question:

Is it expected behavior for the TDO output high level of a MAX 10 device to decrease from approximately 3.3 V to approximately 2.5 V when a USB-Blaster (or USB-Blaster II) is connected, despite VCCIO1B and VTREF both being 3.3 V?

Are there any known characteristics, loading effects, or application notes related to this behavior?

We would appreciate your comments and guidance.