FPGA reset asynchronous or synchronous?

If you have a asyncronious reset, which also clears asynchrone you might end up with some meta-stability after the reset, and you don't want this. You can prevent this by using a synchrone reset, but this gives troubles if you have a reseet affecting the clock, or timing problems. The solution I use is to trigger the reset asynchrone and then clock the clear through two flip-flops to get it synchronised. In this way you have the best of both worlds.