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Altera_Forum
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11 years ago

FPGA reset asynchronous or synchronous?

I normally reset all my d-types using their asynchronous input. I have done this for a long time without any issues. The other day I was chatting to someone else and he said it is best practic...
Altera_Forum's avatar
Altera_Forum
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11 years ago

just have the async reset connected to a synchronous signal, then no problem with timing (or what pierter suggested above).

Altera flops have no sync resets, so their behaviour has to be emulated with a mux. But it will make your code more portable, and slightly easier to read.