FPGA reset asynchronous or synchronous?

There is a dedicated, LAB-wide synchronous reset, so it's not going to use up part of your LUT, but synthesis does try to push LUT logic onto the synchronous reset if it's available, so the net sum is it can make your design larger and slower if you have a synchronous reset. I have worked with users that have switched entire designs from synchronous to asynchronous, and the area savings was <2% and the performance savings was less than normal seed noise, so though I recommend asynchronous, it's not something that usually makes or breaks your design. (I've had users debating if they wanted to convert hundreds of old files that they really don't want to touch, and evaluate it wasn't worth the work).