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Altera_Forum
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11 years ago

FPGA reset asynchronous or synchronous?

I normally reset all my d-types using their asynchronous input. I have done this for a long time without any issues. The other day I was chatting to someone else and he said it is best practic...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Thanks Tricky. How would have though a reset signal could be so interesting :-)

From what you have written does that mean you would use a mux on every flip flop in a design to give them all synchronous reset?