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Does anyone have any comments or advice on this subject?
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The choice of which HDL style to use should be influenced by the underlying architecture of the FPGA, or FPGA resource.
For example, I recall an FPGA component (DSP block in Xilinx I think) that does not have an asynchronous reset. If you tried to code one, you either ended up with an error, or "extra" logic.
The registers in Altera devices have asynchronous reset ports, so you should write your code such that it uses them. The caveat is that you need to synchronize the reset sources to each clock domain in your FPGA, i.e., use the reset synchronizer PietervanderStar posted. Cliff Cummings has several tutorials on synchronizing reset. TimeQuest will analyze your synchronized reset paths via the reset recovery and removal timing.
If you write your code for a synchronous reset, then Quartus will create logic to implement your synchronous reset, i.e., you will needlessly use up LUT inputs. So the "cost" of using an incorrect style, is a larger design, and a potential to increase the combinatorial path in your design.
I'd recommend reading the Cliff Cummings papers on resets ...
http://www.sunburst-design.com/papers/ Cheers,
Dave
Honored Contributor
