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Honored Contributor
Honored ContributorDesign portability on a cyclone
Good morning,
I've got a HDL design which run in RTL simulation. This design run in gate level simulation with time modelisation on a stratix II or an arria II. Howerver, it doesn't work on a cyclone (II or III) FPGA. I don't know what to do ! It's the first time for me that a design work on RTL simulation, on gate level simulation for several device but not on a Cyclone II/III. For information here is the result of the ressource utilization on stratix II :Combinational ALUTs 5,491 / 72,768 ( 8 % )
Dedicated logic registers 4,037 / 72,768 ( 6 % )
Combinational ALUT usage by number of inputs
-- 7 input functions 29
-- 6 input functions 1400
-- 5 input functions 625
-- 4 input functions 600
-- <=3 input functions 2837
Combinational ALUTs by mode
-- normal mode 3957
-- extended LUT mode 29
-- arithmetic mode 1388
-- shared arithmetic mode 117
Logic utilization 7,961 / 72,768 ( 11 % )
-- Difficulty Clustering Design Low
-- Combinational ALUT/register pairs used in final Placement 7168
-- Combinational with no register 3131
-- Register only 1677
-- Combinational with a register 2360
-- Estimated pairs recoverable by pairing ALUTs and registers as design grows -260
-- Estimated Combinational ALUT/register pairs unavailable 1053
-- Unavailable due to unpartnered 7 LUTs 18
-- Unavailable due to unpartnered 6 LUTs 886
-- Unavailable due to unpartnered 5 LUTs 27
-- Unavailable due to LAB-wide signal conflicts 99
-- Unavailable due to LAB input limits 23
Total registers* 4,037 / 75,850 ( 5 % )
-- Dedicated logic registers 4,037 / 72,768 ( 6 % )
-- I/O registers 0 / 3,082 ( 0 % )
ALMs: partially or completely used 4,263 / 36,384 ( 12 % )
Total LABs: partially or completely used 585 / 4,548 ( 13 % )
User inserted logic elements 0
Virtual pins 0
I/O pins 168 / 535 ( 31 % )
-- Clock pins 12 / 16 ( 75 % )
Global signals 2
M512s 0 / 488 ( 0 % )
M4Ks 16 / 408 ( 4 % )
M-RAMs 1 / 4 ( 25 % )
Total block memory bits 223,096 / 4,520,448 ( 5 % )
Total block memory implementation bits 663,552 / 4,520,448 ( 15 % )
DSP block 9-bit elements 4 / 384 ( 1 % )
PLLs 0 / 6 ( 0 % )
Global clocks 2 / 16 ( 13 % )
Regional clocks 0 / 32 ( 0 % )
SERDES transmitters 0 / 118 ( 0 % )
SERDES receivers 0 / 118 ( 0 % )
JTAGs 0 / 1 ( 0 % )
ASMI blocks 0 / 1 ( 0 % )
CRC blocks 0 / 1 ( 0 % )
Remote update blocks 0 / 1 ( 0 % )
Average interconnect usage (total/H/V) 2% / 2% / 2%
Peak interconnect usage (total/H/V) 27% / 27% / 26%
Maximum fan-out node CLK~clkctrl
Maximum fan-out 4076
19 Replies
Altera_Forum--- Quote Start --- During the compilation, I have "approximatily" the same message for the stratix and the cyclone. No interresting warning. I found one warning when I looked at the waves in ModelSim. The message is "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)". That's means I've got an issue with a multiplier ? thanks --- Quote End --- is an "X" in the output of the simulation ? Kind regards GPK- Altera_Forum
During the compilation, I have "approximatily" the same message for the stratix and the cyclone. No interresting warning.
I found one warning when I looked at the waves in ModelSim. The message is "There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)". That's means I've got an issue with a multiplier ? thanks - Altera_Forum--- Quote Start --- The design that I try to implement on a cyclone is a JPEG encoder : http://opencores.org/project,mkjpeg. I have managed to quick compile and test this design on a stratix II but, to make it run on a cyclone seems to be quiet difficult. "the design doesn't react as my RTL simulation " means that the output JPEG file is incorrect when I run a cyclone gate level simulation. However, in RTL simulation and in gate level stratix II simulation the design work properly with a perfect JPEG file. The problem is that I didn't find anything interresting in the warning : it seems to be the same as the StratixII : - Inferred RAM - PINs warning - object assigned a value but never read - pass through logic have been added to match the read-during-write behavior Thank you for your help. (To make the design run on an Altera chip you have to change one thing : headerROM.v : reg[7:0] mem [1023:0] -> reg[7:0] mem [0:622]) Regards --- Quote End --- Hi, what about timing violations ? Did you constrain clocks, input delays etc ... Kind regard GPK
- Altera_Forum
The design that I try to implement on a cyclone is a JPEG encoder : http://opencores.org/project,mkjpeg. I have managed to quick compile and test this design on a stratix II but, to make it run on a cyclone seems to be quiet difficult.
"the design doesn't react as my RTL simulation " means that the output JPEG file is incorrect when I run a cyclone gate level simulation. However, in RTL simulation and in gate level stratix II simulation the design work properly with a perfect JPEG file. --- Quote Start --- What kind of warnings did you get in your Cyclone project ? --- Quote End --- The problem is that I didn't find anything interresting in the warning : it seems to be the same as the StratixII : - Inferred RAM - PINs warning - object assigned a value but never read - pass through logic have been added to match the read-during-write behavior Thank you for your help. (To make the design run on an Altera chip you have to change one thing : headerROM.v : reg[7:0] mem [1023:0] -> reg[7:0] mem [0:622]) Regards - Altera_Forum--- Quote Start --- I think did'nt understand your question... Here is what I've done : I compiled my HDL code for a cyclone II. I have made a gate level simulation with Altera-Modelsim thanks to the .vho and the .sdo files. It doesn't work : the design doesn't react as my RTL simulation. I have done the same with a stratix II and it works : the gate level simulation for the stratix II make the same result as RTL simulation. That's why I think my code can be fit in a FPGA, but it doesn't work on my cylconeII. I've answer to your question ? In anyway, thank you very much for your answer ! --- Quote End --- Hi, can you explain more detailed what you mean with "the design doesn't react as my RTL simulation " ? What kind of warnings did you get in your Cyclone project ? Kind regards GPK
- Altera_Forum
I think did'nt understand your question... Here is what I've done :
I compiled my HDL code for a cyclone II. I have made a gate level simulation with Altera-Modelsim thanks to the .vho and the .sdo files. It doesn't work : the design doesn't react as my RTL simulation. I have done the same with a stratix II and it works : the gate level simulation for the stratix II make the same result as RTL simulation. That's why I think my code can be fit in a FPGA, but it doesn't work on my cylconeII. I've answer to your question ? In anyway, thank you very much for your answer ! - Altera_Forum--- Quote Start --- You right, there are no MRAM on the cyclone. However MRAM cannot be replace by M9K during synthesis ? I'll check wich part of my design use the MRAM in order to move it to M9K. If the fact that I use MRAM can make the design don't work, the same approach can be done for the DSP block ? I mean : there are no DSP block in cyclone ! (I thought that the synthesis use the multiplier with LE to make the same) Am I right ? --- Quote End --- Hi actris, did you run a synthesis for Cyclone devices starting from RTL ? Kind regards GPK
- Altera_Forum
You right, there are no MRAM on the cyclone. However MRAM cannot be replace by M9K during synthesis ?
I'll check wich part of my design use the MRAM in order to move it to M9K. If the fact that I use MRAM can make the design don't work, the same approach can be done for the DSP block ? I mean : there are no DSP block in cyclone ! (I thought that the synthesis use the multiplier with LE to make the same) Am I right ? - Altera_Forum
There is one thing i see ....
--- Quote Start --- M512s 0 / 488 ( 0 % ) M4Ks 16 / 408 ( 4 % ) M-RAMs 1 / 4 ( 25 % ) --- Quote End --- I thought Cyclone II and III have only M9K Memory blocks and no M-RAM, isn't that only available with Stratix devices ? I haven't seen M-RAM on any Cyclone I-III project i have done.
