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The design that I try to implement on a cyclone is a JPEG encoder :
http://opencores.org/project,mkjpeg. I have managed to quick compile and test this design on a stratix II but, to make it run on a cyclone seems to be quiet difficult.
"the design doesn't react as my RTL simulation " means that the output JPEG file is incorrect when I run a cyclone gate level simulation. However, in RTL simulation and in gate level stratix II simulation the design work properly with a perfect JPEG file.
The problem is that I didn't find anything interresting in the warning : it seems to be the same as the StratixII :
- Inferred RAM
- PINs warning
- object assigned a value but never read
- pass through logic have been added to match the read-during-write behavior
Thank you for your help.
(To make the design run on an Altera chip you have to change one thing : headerROM.v : reg[7:0] mem [1023:0] -> reg[7:0] mem [0:622])
Regards
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Hi,
what about timing violations ? Did you constrain clocks, input delays etc ...
Kind regard
GPK
Honored Contributor
