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Altera_Forum
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16 years ago

Design portability on a cyclone

Good morning, I've got a HDL design which run in RTL simulation. This design run in gate level simulation with time modelisation on a stratix II or an arria II. Howerver, it doesn't work on ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

You right, there are no MRAM on the cyclone. However MRAM cannot be replace by M9K during synthesis ?

I'll check wich part of my design use the MRAM in order to move it to M9K.

If the fact that I use MRAM can make the design don't work, the same approach can be done for the DSP block ? I mean : there are no DSP block in cyclone ! (I thought that the synthesis use the multiplier with LE to make the same)

Am I right ?