reduced VCCL_SDM, VCCPLLDIG_SDM on A5E

The SmartVID parts  list  VCCcore and VCCP able to be varied from 0.7 to 0.9V. 

however- VCCL_SDM, VCCPLLDIG_SDM have a specified minimum of 0.78. They require the VCCL_SDM, VCCPLLDIG_SDM  at 0.8V. IE needs extra power plane and power supply regulator.

I need to understand when using  -2V or -3V devices : 

What are the functional  impacts of tying VCCL_SDM, VCCPLLDIG_SDM  to VCCcore ?

What limitations am I likely to encounter at VCCL_SDM, VCCPLLDIG_SDM being at 0.725,  0.7V ?

(SDM and PLL clock speeds I am guessing )

It is accepted that  VCC_HSSI   must remain at datasheet spec.  

(2) How can I vary VCCcore in the power thermal analyser (PTA) ? the TCL commands dont seem to be able to vary these voltages to look at effect of static power consumption. Is there a model in the current PTA to be able to characterise this ?

Reason  for this is to lower static power as much as possible (when the device is not busy - IE clock speeds can be lowered).  In Xilinx, the DSP block cascade Fmax breaks first, and some PLL max F.   

with thanks

glen.