reduced VCCL_SDM, VCCPLLDIG_SDM on A5E

Hi Glen,

---

Part 1 — Tying VCCL_SDM / VCCPLLDIG_SDM to VCCcore on –2V / –3V devices

The short answer is: this is out-of-spec operation and the documentation does not characterize the failure modes, but I can give you the full context of why it's problematic.

The Pin Connection Guidelines are unambiguous about the required supply voltage for VCCL_SDM:

VCCL_SDM is the SDM power supply. For devices with speed grade –1V, –2V, –2E, –3V, and –4S, these pins must be connected to a 0.8-V power supply. Pin Connection Guidelines

The guidelines further state to connect VCCL_SDM to a dedicated 0.8-V power supply. Pin Connection Guidelines

And for VCCPLLDIG_SDM specifically:

VCCPLLDIG_SDM must be sourced from the same regulator as VCCL_SDM, with proper isolation filtering. Pin Connection Guidelines

On –2V and –3V SmartVID devices, VCCcore is PMBus-controlled and will be actively pulled down during the ITD (Initial Trim and Detect) phase and thereafter to the optimal operating point — it is not fixed at 0.8V. Agilex 5 SmartVID standard power devices must be driven by a PMBus-compliant voltage regulator operating in either PMBus master or PMBus slave mode. Power Management User Guide The core voltage is explicitly dynamic. Tying VCCL_SDM to VCCcore means the SDM's own supply rail will track those voltage commands.

At 0.725V or 0.7V, VCCL_SDM would be well below the 0.8V ±3% (≈0.776V minimum) requirement for –2V/–3V parts. Your intuition about SDM operation and PLL behaviour being impacted is correct in principle — the SDM controls configuration, security, and boot, and VCCPLLDIG_SDM powers the SDM's PLL — but the available Pin Connection Guidelines and Power Management documentation do not characterize the specific failure modes or frequency de-rating at those sub-spec voltages. I cannot give you a documented "PLL F_max breaks at X mV" figure for VCCL_SDM, as that is not published. What is documented is that the rail has a hard requirement for 0.8V for these speed grades, and operating below it is unsupported.

One practical note: you do have the option to connect VCCL_SDM, VCC_HSSI, VCC_IO_SDM, and VCCL_ADC_SDM to the same regulator as VCCPLLDIG2_HPS VCC and VCCP when the power rails require the same voltage level, and you may also connect VCCPLLDIG1_HPS, VCCPLLDIG2_HPS, and VCCPLLDIG_SDM to shared VCC, VCCP, and VCCL_HPS power planes with proper isolation filtering. Pin Connection Guidelines This sharing is permitted when those rails are at the same level — but that level must still be 0.8V for –2V/–3V devices. It doesn't eliminate the separate 0.8V requirement; it just allows regulator sharing with proper filtering.

---

Part 2 — Varying VCCcore voltage in the PTA for static power analysis

The Power and Thermal Calculator for Agilex 5 devices provides a current and power estimate based on various conditions such as room temperature and nominal voltage. Power Management User Guide The Power and Thermal Calculator results for Agilex 5 devices are based on preliminary simulated data. Power Management User Guide

The PTA Tcl API (the ::quartus::pta package) exposes edit, get_results, recalculate_power, and related commands for modifying resource-level parameters (e.g. RAM block count, clock frequency, enable percentage). However, the documented PTA Tcl properties visible in the available documentation are design-resource-level inputs — there is no documented edit property key for sweeping VCCcore or VCCL_SDM voltage to characterise static power versus supply voltage in the current PTA model. The calculator works at nominal voltage.

For post-fit analysis, Altera recommends switching from the Power and Thermal Calculator to the Power Analyzer in Quartus Prime once your design is available, because the Power Analyzer produces more accurate results — it has more detailed information about your design, including routing and configuration information about all the resources in your design. Power Management User Guide Agilex™ 5 FPGAs and SoCs The Quartus Prime Power Analyzer does have voltage/temperature corner options in the Power Analysis settings (Process, Voltage, Temperature — PVT), which is the proper place to explore static power sensitivity to supply voltage. That's the tool to reach for if you want to model reduced VCC static power at lower activity states; the standalone PTA is not the right vehicle for a VCC sweep.

In terms of your broader goal of reducing static power at low activity: the SmartVID feature compensates for process variation by narrowing the process distribution using voltage adaptation, Power Management User Guide which is the primary mechanism for VCC reduction on –1V through –3V parts. Reducing clock frequencies will cut dynamic power directly, but static power reduction is best modelled in Quartus Prime Pro's Power Analyzer with appropriate PVT corner settings.

rgards

Farabi