3.3 V Connection to ADC_VREF When Replacing a MAX 10 SC Device with an SA Device

Hello, this is a very common concern when swapping between SC and SA variants in the same package.

What the Pin Connection Guidelines say:

The ADC_VREF pin is the ADC voltage reference input. The guidelines state you should tie it to an external accurate voltage reference source; if you are not using the external reference, this pin should be left as no connect (NC). MAX 10 FPGA Device Family Pin Connection Guidelines

That is the formal recommendation. However, looking at the electrical specs for this specific scenario:

Electrical impact of connecting 3.3 V to ADC_VREF:

• The ADC_VREF pin leakage current in single supply mode has a maximum of 10 µA. MAX 10 FPGA Device Datasheet Since the 10M08SAU169C8G is a single-supply SA device, this is the applicable spec. Connecting 3.3 V to ADC_VREF will source at most 10 µA from your 3.3 V rail — that is the only electrical load imposed on that net.
• For single-supply devices, the external reference voltage can be up to 3.63 V. Modular ADC Core Parameters Settings 3.3 V is comfortably within this range, so the voltage level itself is not out-of-spec for that pin.

Functional impact if the ADC is not used:

Each ADC block in MAX 10 devices can independently use an internal or external voltage reference. MAX 10 Analog to Digital Converter User Guide If you do not instantiate the ADC IP in your design and select the internal reference (or simply leave the ADC unused), the ADC_VREF pin being driven to 3.3 V will not affect FPGA fabric logic operation. The pin will simply present a leakage load as noted above.

Bottom line:

From a pure electrical standpoint, 3.3 V on ADC_VREF is within the single-supply device's specified pin voltage range, and the only consequence is a ≤10 µA leakage draw. The NC recommendation in the Pin Connection Guidelines is the conservative design practice when the external reference is intentionally unused — it is not an absolute prohibition against having a voltage present on the pin. If your design does not instantiate the ADC or does not select external VREF, device functionality should not be affected.

That said, the formal guideline does say NC for the unused-reference case, so if your design review process or qualification requirements mandate strict adherence to the Pin Connection Guidelines, a PCB revision to add a DNP (do-not-populate) series resistor or leave the trace open would be the fully compliant path. For most applications, however, the 3.3 V connection as-is is electrically benign for this pin on the SA single-supply variant.

regards,

Farabi

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Thank you very much.