Honored Contributor
Honored ContributorI think did'nt understand your question... Here is what I've done :
I compiled my HDL code for a cyclone II. I have made a gate level simulation with Altera-Modelsim thanks to the .vho and the .sdo files. It doesn't work : the design doesn't react as my RTL simulation. I have done the same with a stratix II and it works : the gate level simulation for the stratix II make the same result as RTL simulation. That's why I think my code can be fit in a FPGA, but it doesn't work on my cylconeII. I've answer to your question ? In anyway, thank you very much for your answer !
