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Altera_Forum's avatar
Altera_Forum
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16 years ago

Design portability on a cyclone

Good morning, I've got a HDL design which run in RTL simulation. This design run in gate level simulation with time modelisation on a stratix II or an arria II. Howerver, it doesn't work on ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

There is one thing i see ....

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M512s 0 / 488 ( 0 % )

M4Ks 16 / 408 ( 4 % )

M-RAMs 1 / 4 ( 25 % )

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I thought Cyclone II and III have only M9K Memory blocks and no M-RAM, isn't that only available with Stratix devices ?

I haven't seen M-RAM on any Cyclone I-III project i have done.