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Altera_Forum's avatar
Altera_Forum
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13 years ago

DDR3 Uniphy External interface

Hi,

I would like to ask question regarding the interfaces of DDR3 controller. I tried to do simple ddr3_uniphy in Cyclone V GT FPGA using Qsys. After I generate the Qsys and add the symbol in Quartus II, I was able to produce a topblock as staed in attached photo. My concern is regarding the differential interfaces going to ddr3 device. The ck and dqs.... In topblock bdf I have only 1 pair of differential Clock (ck and ckn) and two pair of differential DQS(dqs[1] and dqs_n[1], and dqs[0] and dqs_n[0]). This should be the correct one as the external DDR3 devices has only 1 pair of diff clock and 2 pair of DQS.

However when i try to assign pins, there are 2 pair of diff clock and 4 pair of DQS. See the attached photo pin assign. I'm wondering if this is a bug in this version.

An external DDR3 cannot have 2 differential clock and 4 differential DQS.

Moreover, what is oct_rzqin? Where/what should I connect to it?https://www.alteraforum.com/forum/attachment.php?attachmentid=7494 https://www.alteraforum.com/forum/attachment.php?attachmentid=7495

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    So this happened to me not to long ago as well. What happened is that when you switch the pin to a differential pin (probably by running the tcl script) it automatically created its differential counter part instead of using the already created pin. this means that memory_mem_ck created memory_mem_ck(n) as its differential pair instead of using the memory_ck_n pin. To solve this you can change the differential pair in the right column of the memory_mem_ck to the memeory_mem_ck_n. Do this for all your differential pins. the extra created pin should get removed automatically

    For you oct_rzqin i am not familiar with that because i was using a ddr2 controller and there was not such pin.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hi,

    Thanks... I was successful doing it in memory_mem_ck. But for the memory_mem_dqs, I got no luck. It keep on coming back to its original name after I change it.

    Regards
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Humm that's really weird. Because i had no problem changing all of mine. Maybe try changing the I/O standard and switching it back. It could also be because you did a compilation already and it already fitted the pin. Maybe try deleting the pin and re adding them. Hopefully you can figure it out because like i said mine had no problem for all of the differential pins.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    hi,

    I had notice that if the pin name has ["any number"] Ex. dqs[1] or dqs[0], you will have no luck editing the differential pair as I did, it keeps on coming back.

    I tried to change the memory_mem_ck name to memory_mem_ck[0] and do everything again to confirm. It confirms that with this ['number'] on the name, it cannot change its differential pair name on differential pair column. It will keep coming back to its original no matter how you try.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    no it has nothing to do with being an vector. it should still work because i was able to do it no problem. here is the proof. It was doing the same thing but all i had to do is close and re open the project and that was nothing was compiled and it worked like a charm.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hi,

    I have exactly the same issue with additional pairs of differential signal for CLK and DQS. I tried to edit the differential pair in pin mapping but it doesn't make changes. Have you find a way to solve this problem? Thanks for any help in advance.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    You have to change the IO standard of the DQS and CLK pins from "Differential 1.5-V SSTL Class I" to "SSTL-15 Class 1". Then you have to assign your pins location. Then you run the "analysis & synthesis". When it's finished run the tcl script "pin_assignment.tcl".

    Then recompile the project and it should work.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hi arisrama22,

    For the oct_rzqin pin, check out your board pin_out list (or the board schematics).

    It's an on-chip termination pin which goes to a resistor.

    (for my case : Cyclone V GX, dev kit, PIN_AK13)

    Otherwise, "actris" 's solution is a good one to prevent pin settings problem for DDR3.

    regards.

    regards,