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Altera_Forum's avatar
Altera_Forum
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13 years ago

DDR3 Uniphy External interface

Hi, I would like to ask question regarding the interfaces of DDR3 controller. I tried to do simple ddr3_uniphy in Cyclone V GT FPGA using Qsys. After I generate the Qsys and add the symbol in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Hi,

Thanks... I was successful doing it in memory_mem_ck. But for the memory_mem_dqs, I got no luck. It keep on coming back to its original name after I change it.

Regards