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Altera_Forum
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13 years ago

DDR3 Uniphy External interface

Hi, I would like to ask question regarding the interfaces of DDR3 controller. I tried to do simple ddr3_uniphy in Cyclone V GT FPGA using Qsys. After I generate the Qsys and add the symbol in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi arisrama22,

For the oct_rzqin pin, check out your board pin_out list (or the board schematics).

It's an on-chip termination pin which goes to a resistor.

(for my case : Cyclone V GX, dev kit, PIN_AK13)

Otherwise, "actris" 's solution is a good one to prevent pin settings problem for DDR3.

regards.

regards,