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Altera_Forum
Honored Contributor
Honored ContributorDDR3 Uniphy External interface
Hi, I would like to ask question regarding the interfaces of DDR3 controller. I tried to do simple ddr3_uniphy in Cyclone V GT FPGA using Qsys. After I generate the Qsys and add the symbol in...
Altera_ForumHonored Contributor
Honored ContributorSorry i could not be more help but you can take a look at these tutorial that might be able to help you find the problem
http://www.altera.com/education/training/courses/odsw1107 http://www.altera.com/education/training/courses/odsw1108
