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Altera_Forum's avatar
Altera_Forum
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13 years ago

DDR3 Uniphy External interface

Hi, I would like to ask question regarding the interfaces of DDR3 controller. I tried to do simple ddr3_uniphy in Cyclone V GT FPGA using Qsys. After I generate the Qsys and add the symbol in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

You have to change the IO standard of the DQS and CLK pins from "Differential 1.5-V SSTL Class I" to "SSTL-15 Class 1". Then you have to assign your pins location. Then you run the "analysis & synthesis". When it's finished run the tcl script "pin_assignment.tcl".

Then recompile the project and it should work.