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Altera_Forum
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13 years ago

DDR3 Uniphy External interface

Hi, I would like to ask question regarding the interfaces of DDR3 controller. I tried to do simple ddr3_uniphy in Cyclone V GT FPGA using Qsys. After I generate the Qsys and add the symbol in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi,

I have exactly the same issue with additional pairs of differential signal for CLK and DQS. I tried to edit the differential pair in pin mapping but it doesn't make changes. Have you find a way to solve this problem? Thanks for any help in advance.