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Altera_Forum
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12 years ago

DDR3 Uniphy External interface

Hi, I would like to ask question regarding the interfaces of DDR3 controller. I tried to do simple ddr3_uniphy in Cyclone V GT FPGA using Qsys. After I generate the Qsys and add the symbol in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

So this happened to me not to long ago as well. What happened is that when you switch the pin to a differential pin (probably by running the tcl script) it automatically created its differential counter part instead of using the already created pin. this means that memory_mem_ck created memory_mem_ck(n) as its differential pair instead of using the memory_ck_n pin. To solve this you can change the differential pair in the right column of the memory_mem_ck to the memeory_mem_ck_n. Do this for all your differential pins. the extra created pin should get removed automatically

For you oct_rzqin i am not familiar with that because i was using a ddr2 controller and there was not such pin.