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Altera_Forum
Honored Contributor
Honored ContributorDDR3 Uniphy External interface
Hi, I would like to ask question regarding the interfaces of DDR3 controller. I tried to do simple ddr3_uniphy in Cyclone V GT FPGA using Qsys. After I generate the Qsys and add the symbol in...
Altera_ForumHonored Contributor
Honored Contributorno it has nothing to do with being an vector. it should still work because i was able to do it no problem. here is the proof. It was doing the same thing but all i had to do is close and re open the project and that was nothing was compiled and it worked like a charm.
