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Altera_Forum's avatar
Altera_Forum
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13 years ago

DDR3 Uniphy External interface

Hi, I would like to ask question regarding the interfaces of DDR3 controller. I tried to do simple ddr3_uniphy in Cyclone V GT FPGA using Qsys. After I generate the Qsys and add the symbol in...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Humm that's really weird. Because i had no problem changing all of mine. Maybe try changing the I/O standard and switching it back. It could also be because you did a compilation already and it already fitted the pin. Maybe try deleting the pin and re adding them. Hopefully you can figure it out because like i said mine had no problem for all of the differential pins.