Forum Discussion
Honored ContributorCyclone V SoC - Shared Memory Controller
Hi @all,
I have a problem generating a Design with connection from FPGA to the HPS-Memorycontroller. I set up a QSYS-System with the connections and now try to get data from this Memory. I have seen something like that there must be set some registers in the HPS to open the connection, (like with the HPS<->FPGA bridges), but I don't get the preloader generated by my design run correctly. And if I set the registervalues in HPS by hand, nothing happend on this interface. Has anyone set up a system with the shared memorycontroller working and could give me a hint to the right direction?51 Replies
Altera_Forumwaitrequest is an output of the memory controller, so i'm not sure the F2H port would be the problem. can you check the status signals of the memory controller to see if it has passed calibration?
- Altera_Forum--- Quote Start --- Since I'm more of a hardware person my approach to this would be to have a soft DMA sitting in the FPGA that accesses the FPGA-to-SDRAM interface to move the data. I'm not sure what your end goal will be but is it possible for the FPGA to master the data directory by accessing the FPGA-to-SDRAM interface without the copy? Based on the numbers you are seeing it sounds like memcpy doesn't make use of the DMA in the HPS. Even if it did use the HPS DMA, I would expect much more bandwidth to be possible if the FPGA read the data directly from the FPGA-to-HPS interface though. --- Quote End --- Hi BadOmen, I have tried to build a simple FPGA block that interrogates the SDRAM on the HPS via the F2H SDRAM port. I'm using a module from an example on rocketboards (http://www.rocketboards.org/foswiki/view/projects/myfirstmodule) that allocates a section of SDRAM on the HPS for the purposes of reading/writing via the FPGA. However on the FPGA side I cannot get a response to requests for memory reads, when viewed in signaltap, the waitrequest signal of the Avalon_MM bus is always high. Do you know the reason for this and the solution? Is it possible that I need to do something in software to enable the F2H port on the HPS SDRAM.
- Altera_Forum--- Quote Start --- Since I'm more of a hardware person my approach to this would be to have a soft DMA sitting in the FPGA that accesses the FPGA-to-SDRAM interface to move the data. I'm not sure what your end goal will be but is it possible for the FPGA to master the data directory by accessing the FPGA-to-SDRAM interface without the copy? Based on the numbers you are seeing it sounds like memcpy doesn't make use of the DMA in the HPS. Even if it did use the HPS DMA, I would expect much more bandwidth to be possible if the FPGA read the data directly from the FPGA-to-HPS interface though. --- Quote End --- Hi BadOmen, I have tried to build a simple FPGA block that interrogates the SDRAM on the HPS via the F2H SDRAM port. I'm using a module from an example on rocketboards (http://www.rocketboards.org/foswiki/view/projects/myfirstmodule) that allocates a section of SDRAM on the HPS for the purposes of reading/writing via the FPGA. However on the FPGA side I cannot get a response to requests for memory reads, when viewed in signaltap, the waitrequest signal of the Avalon_MM bus is always high. Do you know the reason for this and the solution? Is it possible that I need to do something in software to enable the F2H port on the HPS SDRAM.
- Altera_Forum
Since I'm more of a hardware person my approach to this would be to have a soft DMA sitting in the FPGA that accesses the FPGA-to-SDRAM interface to move the data. I'm not sure what your end goal will be but is it possible for the FPGA to master the data directory by accessing the FPGA-to-SDRAM interface without the copy?
Based on the numbers you are seeing it sounds like memcpy doesn't make use of the DMA in the HPS. Even if it did use the HPS DMA, I would expect much more bandwidth to be possible if the FPGA read the data directly from the FPGA-to-HPS interface though. - Altera_Forum
It seems Voroshazi and I are trying to do a very similar thing. I have also been working on moving data from the HPS to the FPGA SDRAM across the HPS2FPGA bridge. I too have been able to achieve this but have the same issue in that the throughput I am getting is in the order of 58MB/sec (by memcpy from HPS SDRAM to FPGA SDRAM). I'm not using a DMA either and wondered if you had been able to achieve better than this (I need at least 80MB/sec for my application)?
does anybody have any insight as to why the data rate is so low? I was expecting it to be much faster. - Altera_Forum
I don't know of any designs that DMA data between the FPGA fabric and HPS using the DMA controller built into the HPS. Up on Rocketboards there should be a PCIe design that DMAs data using a soft DMA controll in the FPGA between the two FPGAs over PCIe. If you don't require a lot of throughput then you can use the HPS DMA controller. If you require a lot of throughput then a soft DMA in the FPGA fabric will make more sense since it will not cycle through multiple channels like the HPS DMA does.
The h2f_reset is provided so that you can trigger a reset into the FPGA fabric from the HPS. It is optional to use but typically if you reset the HPS you'll want to reset FPGA peripherals connected to the HPS as well. The reason why I brought up the address span expander is because the Nios II masters only provide 32-bits of addressing. So if you connect Nios II to any of the HPS slave ports you won't have any address bits left over to connect Nios II to anything else. That's why the bridge between the Nios II master and HPS is necessary. - Altera_Forum
Dear BadOmen,
Here is a feedback for your comments as I promised. According to your previous post I have also managed to access now the FPGA SDRAM / internal BRAM from the HPS portion (ARM side) at HWLib level. The key was to release the bridges from reset (init_bridge in hwlib.c). However, without DMA I have measured only 10 - 15 MB/s memory throughput (between ARM vs. FPGA memory) across HPS2FPGA bridge. Do you suggest any reference design, which integrates (FW/SW) and uses DMA? What is the role the h2f_reset signal in HPS (cylcone V handbook gives a few info)? Because as I experienced if I left this signal unconnected in qsys I can use both FPGA memory and HPS memory in a same FW design? The debounce circuit is also eliminated from golden HW/SW reference design. "Address Span Expander" bridge will be a good IP in the future, but I set all memory address spaces to a narrower size in order to be accessed by a 32-bit addresses of Nios II processor. Regards, ZS.V. - Altera_Forum
I don't know all the details but there is an issue with the way the preloader sets up the FPGA-to-SDRAM interfaces. So it's a software fix to resolve the issue. The issue only affects the read performance, so if you are seeing write performance issues then it is most likely something else going on.
- Altera_Forum--- Quote Start --- Also so that you don't spend time debugging a known issue, there is a known issue with the throughput between the FPGA and the HPS. This issue will be corrected in the next update. --- Quote End --- Can you elaborate more on this? I have some problems with the throughput. Are you referring to an update of Quartus, EDS, or the kernel?
- Altera_Forum
Dear BadOmen,
Thank you for your answer. I will try it and give some feed-back. Regards, ZS.V.
