Cyclone V SoC - Shared Memory Controller

Since I'm more of a hardware person my approach to this would be to have a soft DMA sitting in the FPGA that accesses the FPGA-to-SDRAM interface to move the data. I'm not sure what your end goal will be but is it possible for the FPGA to master the data directory by accessing the FPGA-to-SDRAM interface without the copy?

Based on the numbers you are seeing it sounds like memcpy doesn't make use of the DMA in the HPS. Even if it did use the HPS DMA, I would expect much more bandwidth to be possible if the FPGA read the data directly from the FPGA-to-HPS interface though.